URoT · FPGA-PUF

Hardware Root-of-Trust Telemetry Console

Research · Jaswanth

OFFLINE

ONLINE 0

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Temperature

—°C

Authenticated sensor field

Humidity

—%RH

Signed payload field

PUF Authentication

—

Masked Hamming gate · Eq.(22)

Hamming Distance

—/ θ —

d_M(R*,R′) vs threshold

Stable Bits (mask)

—/128

Unanimous bits · Eq.(19,20)

Msg Counter

—

Monotonic replay nonce · Eq.(30)

Auth Latency

—ms

UART + HMAC + HTTPS end-to-end

Auth Success Rate

—%

0 frames verified

📈

Authenticated Telemetry Stream

HMAC-SHA-256 verified · 15 s

▦

FPGA Fabric · Live Data Flow

GW1NR-9 @ 27 MHz

RO BANK 32

LUT 940 (10.9%)

FF 814 (12.6%)

WINDOW 65 536 cyc

∿

Ring-Oscillator Bank

32 × RO

7-stage chain (×16)9-stage chain (×16)

Mean Frequency190.2 MHz

σ (per-instance)2.4 MHz

Pair Δf → bitsign(N_a − N_b)

◎

PUF Quality Metrics

vs ideal

49.6%

Uniqueness

49.7%

Uniformity

99.0%

Reliability

1.0%

Resid. BER

Equal-Error Rate< 1×10⁻³

FAR / FRR<1e-13 / <1e-4

Bit-aliasing indexBA = 0.078

Min-entropy H∞(R|H)≥ 121 bits

🛡

Threat Model · Defense

4 / 4 defeated

⬡

Clone Attack

Root key bound to FPGA gate-delay variation

DEFEATED

↻

Replay Attack

Monotonic counter · Eq.(30) rejects c ≤ c_max

DEFEATED

≈

Impersonation

HMAC unforgeable without PUF-derived key K

DEFEATED

◊

Modeling Attack

Sign-only output · single lifetime challenge C₀

DEFEATED

G1 UnforgeabilityG2 UnclonabilityG3 Replay-resistanceG4 Helper-data conf.

🔑

Cryptographic Binding

5-stage protocol

Device ID—

Challenge C₀0123…3210

Root digest—

K = SHA-256( label ‖ C ‖ R* ‖ M ) (25)

Outbound HMAC-SHA-256 signature σ:

awaiting frame…

Canonical message m = ID‖c‖τ‖h‖a‖S‖d‖θ:

—

⚖

Hamming-Distance Separation

5 000 MC trials

Intra-device (genuine)μ ≈ 5.8 bits

Inter-device (impostor)μ ≈ 63.5 bits

Operating threshold θ13 bits · void region

▶

Verifier Event Log

jaswanthfpga.online

▤

FPGA Resource Utilization

GW1NR-9

Clock27 MHz · +slack

Static / Dynamic power5 mW / 38 mW

User I/O pins9 / 71

BOM cost< USD 18

🌡

Reliability vs Temperature

−20 → 80 °C

Raw PUF (peak)≈ 9% BER

After 5-vote + mask≤ 1.7% BER

◔

Authentication ROC / FAR-FRR

Eq.(23,24)

Operating point τ = θ/n≈ 0.10

Separation margin> 50 bits

⛓

End-to-End Root-of-Trust Pipeline

idle

STAGE 01

CRP Acquisition

5× enroll / 3× auth RO sweeps over UART @115 200

STAGE 02

Helper-Data Mask

Majority vote → R*, unanimity → stable-bit mask M

STAGE 03

Key Derivation

K = SHA-256(label‖C‖R*‖M) · 256-bit root

STAGE 04

Replay Binding

Monotonic counter c bound into canonical message m

STAGE 05

Verifier Check

σ = HMAC_K(m) reconstructed & validated on cloud

▥

Enrolled Device Fleet

0 devices

Status	Device ID	Board	Stable Bits	Auth	Counter	Last Seen

An FPGA Ring-Oscillator PUF Hardware Root-of-Trust for Authenticated IoT Telemetry with HMAC-SHA-256 Cryptographic Binding
32-instance RO-PUF on Gowin GW1NR-9 (Tang Nano 9K) + ESP32-C3 · 128-bit response · 30-equation cryptographic binding
Research & design by Jaswanth
monitor idle

Awaiting Secure Device Handshake

Authenticated Telemetry Stream

FPGA Fabric · Live Data Flow

Ring-Oscillator Bank

PUF Quality Metrics

Threat Model · Defense

Cryptographic Binding

Hamming-Distance Separation

Verifier Event Log

FPGA Resource Utilization

Reliability vs Temperature

Authentication ROC / FAR-FRR

End-to-End Root-of-Trust Pipeline

Enrolled Device Fleet